Index: radeon/atombios_encoders.c
===================================================================
RCS file: /cvs/src/sys/dev/pci/drm/radeon/atombios_encoders.c,v
retrieving revision 1.17
diff -u -p -r1.17 atombios_encoders.c
--- radeon/atombios_encoders.c	24 Feb 2022 12:49:47 -0000	1.17
+++ radeon/atombios_encoders.c	23 Jan 2023 00:24:52 -0000
@@ -202,6 +202,9 @@ void radeon_atom_backlight_init(struct r
 	    !dmi_match(DMI_PRODUCT_NAME, "iMac12,1"))
 		return;
 
+	if (dmi_match(DMI_PRODUCT_NAME, "iMac11,1"))
+		return;
+
 	if (!radeon_encoder->enc_priv)
 		return;
 
@@ -2187,12 +2190,13 @@ int radeon_atom_pick_dig_encoder(struct 
 	}
 
 	/*
-	 * On DCE32 any encoder can drive any block so usually just use crtc id,
-	 * but Apple thinks different at least on iMac10,1, so there use linkb,
-	 * otherwise the internal eDP panel will stay dark.
+	 * On DCE31 any encoder can drive any block so usually just use crtc id,
+	 * but Apple thinks different at least on iMac10,1 and iMac11,1, so
+	 * there use linkb, otherwise the internal eDP panel will stay dark.
 	 */
-	if (ASIC_IS_DCE32(rdev)) {
-		if (dmi_match(DMI_PRODUCT_NAME, "iMac10,1"))
+	if (ASIC_IS_DCE31(rdev)) {
+		if (dmi_match(DMI_PRODUCT_NAME, "iMac10,1") ||
+		    dmi_match(DMI_PRODUCT_NAME, "iMac11,1"))
 			enc_idx = (dig->linkb) ? 1 : 0;
 		else
 			enc_idx = radeon_crtc->crtc_id;
Index: radeon/radeon.h
===================================================================
RCS file: /cvs/src/sys/dev/pci/drm/radeon/radeon.h,v
retrieving revision 1.27
diff -u -p -r1.27 radeon.h
--- radeon/radeon.h	14 Jan 2022 06:53:15 -0000	1.27
+++ radeon/radeon.h	23 Jan 2023 00:24:52 -0000
@@ -2711,6 +2711,7 @@ void r100_pll_errata_after_index(struct 
 			    (rdev->family == CHIP_RS740)  ||	\
 			    (rdev->family >= CHIP_R600))
 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
+#define ASIC_IS_DCE31(rdev) ((rdev->family >= CHIP_RV770))
 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
Index: radeon/radeon_display.c
===================================================================
RCS file: /cvs/src/sys/dev/pci/drm/radeon/radeon_display.c,v
retrieving revision 1.24
diff -u -p -r1.24 radeon_display.c
--- radeon/radeon_display.c	14 Jan 2022 06:53:15 -0000	1.24
+++ radeon/radeon_display.c	23 Jan 2023 00:24:52 -0000
@@ -864,76 +864,66 @@ static bool radeon_setup_enc_conn(struct
 }
 
 /* avivo */
+static void avivo_get_fb_div(struct radeon_pll *pll,
+			     u32 target_clock,
+			     u32 post_div,
+			     u32 ref_div,
+			     u32 *fb_div,
+			     u32 *frac_fb_div)
+{
+	u32 tmp = post_div * ref_div;
 
-/**
- * avivo_reduce_ratio - fractional number reduction
- *
- * @nom: nominator
- * @den: denominator
- * @nom_min: minimum value for nominator
- * @den_min: minimum value for denominator
- *
- * Find the greatest common divisor and apply it on both nominator and
- * denominator, but make nominator and denominator are at least as large
- * as their minimum values.
- */
-static void avivo_reduce_ratio(unsigned *nom, unsigned *den,
-			       unsigned nom_min, unsigned den_min)
+	tmp *= target_clock;
+	*fb_div = tmp / pll->reference_freq;
+	*frac_fb_div = tmp % pll->reference_freq;
+
+        if (*fb_div > pll->max_feedback_div)
+		*fb_div = pll->max_feedback_div;
+        else if (*fb_div < pll->min_feedback_div)
+                *fb_div = pll->min_feedback_div;
+}
+
+static u32 avivo_get_post_div(struct radeon_pll *pll,
+			      u32 target_clock)
 {
-	unsigned tmp;
+	u32 vco, post_div, tmp;
 
-	/* reduce the numbers to a simpler ratio */
-	tmp = gcd(*nom, *den);
-	*nom /= tmp;
-	*den /= tmp;
-
-	/* make sure nominator is large enough */
-	if (*nom < nom_min) {
-		tmp = DIV_ROUND_UP(nom_min, *nom);
-		*nom *= tmp;
-		*den *= tmp;
+	if (pll->flags & RADEON_PLL_USE_POST_DIV)
+		return pll->post_div;
+
+	if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) {
+		if (pll->flags & RADEON_PLL_IS_LCD)
+			vco = pll->lcd_pll_out_min;
+		else
+			vco = pll->pll_out_min;
+	} else {
+		if (pll->flags & RADEON_PLL_IS_LCD)
+			vco = pll->lcd_pll_out_max;
+		else
+			vco = pll->pll_out_max;
 	}
 
-	/* make sure the denominator is large enough */
-	if (*den < den_min) {
-		tmp = DIV_ROUND_UP(den_min, *den);
-		*nom *= tmp;
-		*den *= tmp;
+	post_div = vco / target_clock;
+	tmp = vco % target_clock;
+
+	if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) {
+		if (tmp)
+			post_div++;
+	} else {
+		if (!tmp)
+			post_div--;
 	}
-}
 
-/**
- * avivo_get_fb_ref_div - feedback and ref divider calculation
- *
- * @nom: nominator
- * @den: denominator
- * @post_div: post divider
- * @fb_div_max: feedback divider maximum
- * @ref_div_max: reference divider maximum
- * @fb_div: resulting feedback divider
- * @ref_div: resulting reference divider
- *
- * Calculate feedback and reference divider for a given post divider. Makes
- * sure we stay within the limits.
- */
-static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div,
-				 unsigned fb_div_max, unsigned ref_div_max,
-				 unsigned *fb_div, unsigned *ref_div)
-{
-	/* limit reference * post divider to a maximum */
-	ref_div_max = max(min(100 / post_div, ref_div_max), 1u);
+	if (post_div > pll->max_post_div)
+		post_div = pll->max_post_div;
+	else if (post_div < pll->min_post_div)
+		post_div = pll->min_post_div;
 
-	/* get matching reference and feedback divider */
-	*ref_div = min(max(den/post_div, 1u), ref_div_max);
-	*fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den);
-
-	/* limit fb divider to its maximum */
-	if (*fb_div > fb_div_max) {
-		*ref_div = (*ref_div * fb_div_max)/(*fb_div);
-		*fb_div = fb_div_max;
-	}
+	return post_div;
 }
 
+#define MAX_TOLERANCE 10
+
 /**
  * radeon_compute_pll_avivo - compute PLL paramaters
  *
@@ -956,138 +946,55 @@ void radeon_compute_pll_avivo(struct rad
 			      u32 *ref_div_p,
 			      u32 *post_div_p)
 {
-	unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ?
-		freq : freq / 10;
-
-	unsigned fb_div_min, fb_div_max, fb_div;
-	unsigned post_div_min, post_div_max, post_div;
-	unsigned ref_div_min, ref_div_max, ref_div;
-	unsigned post_div_best, diff_best;
-	unsigned nom, den;
-
-	/* determine allowed feedback divider range */
-	fb_div_min = pll->min_feedback_div;
-	fb_div_max = pll->max_feedback_div;
-
-	if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
-		fb_div_min *= 10;
-		fb_div_max *= 10;
-	}
+       u32 target_clock = freq / 10;
+       u32 post_div = avivo_get_post_div(pll, target_clock);
+       u32 ref_div = pll->min_ref_div;
+       u32 fb_div = 0, frac_fb_div = 0, tmp;
 
-	/* determine allowed ref divider range */
 	if (pll->flags & RADEON_PLL_USE_REF_DIV)
-		ref_div_min = pll->reference_div;
-	else
-		ref_div_min = pll->min_ref_div;
-
-	if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV &&
-	    pll->flags & RADEON_PLL_USE_REF_DIV)
-		ref_div_max = pll->reference_div;
-	else if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP)
-		/* fix for problems on RS880 */
-		ref_div_max = min(pll->max_ref_div, 7u);
-	else
-		ref_div_max = pll->max_ref_div;
-
-	/* determine allowed post divider range */
-	if (pll->flags & RADEON_PLL_USE_POST_DIV) {
-		post_div_min = pll->post_div;
-		post_div_max = pll->post_div;
-	} else {
-		unsigned vco_min, vco_max;
+               ref_div = pll->reference_div;
 
-		if (pll->flags & RADEON_PLL_IS_LCD) {
-			vco_min = pll->lcd_pll_out_min;
-			vco_max = pll->lcd_pll_out_max;
-		} else {
-			vco_min = pll->pll_out_min;
-			vco_max = pll->pll_out_max;
+       if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
+               avivo_get_fb_div(pll, target_clock, post_div, ref_div, &fb_div,
+ &frac_fb_div);
+               frac_fb_div = (100 * frac_fb_div) / pll->reference_freq;
+               if (frac_fb_div >= 5) {
+                       frac_fb_div -= 5;
+                       frac_fb_div = frac_fb_div / 10;
+                       frac_fb_div++;
 		}
 
-		if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
-			vco_min *= 10;
-			vco_max *= 10;
+               if (frac_fb_div >= 10) {
+                       fb_div++;
+                       frac_fb_div = 0;
 		}
-
-		post_div_min = vco_min / target_clock;
-		if ((target_clock * post_div_min) < vco_min)
-			++post_div_min;
-		if (post_div_min < pll->min_post_div)
-			post_div_min = pll->min_post_div;
-
-		post_div_max = vco_max / target_clock;
-		if ((target_clock * post_div_max) > vco_max)
-			--post_div_max;
-		if (post_div_max > pll->max_post_div)
-			post_div_max = pll->max_post_div;
-	}
-
-	/* represent the searched ratio as fractional number */
-	nom = target_clock;
-	den = pll->reference_freq;
-
-	/* reduce the numbers to a simpler ratio */
-	avivo_reduce_ratio(&nom, &den, fb_div_min, post_div_min);
-
-	/* now search for a post divider */
-	if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP)
-		post_div_best = post_div_min;
-	else
-		post_div_best = post_div_max;
-	diff_best = ~0;
-
-	for (post_div = post_div_min; post_div <= post_div_max; ++post_div) {
-		unsigned diff;
-		avivo_get_fb_ref_div(nom, den, post_div, fb_div_max,
-				     ref_div_max, &fb_div, &ref_div);
-		diff = abs(target_clock - (pll->reference_freq * fb_div) /
-			(ref_div * post_div));
-
-		if (diff < diff_best || (diff == diff_best &&
-		    !(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) {
-
-			post_div_best = post_div;
-			diff_best = diff;
-		}
-	}
-	post_div = post_div_best;
-
-	/* get the feedback and reference divider for the optimal value */
-	avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, ref_div_max,
-			     &fb_div, &ref_div);
-
-	/* reduce the numbers to a simpler ratio once more */
-	/* this also makes sure that the reference divider is large enough */
-	avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min);
-
-	/* avoid high jitter with small fractional dividers */
-	if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) {
-		fb_div_min = max(fb_div_min, (9 - (fb_div % 10)) * 20 + 50);
-		if (fb_div < fb_div_min) {
-			unsigned tmp = DIV_ROUND_UP(fb_div_min, fb_div);
-			fb_div *= tmp;
-			ref_div *= tmp;
-		}
-	}
-
-	/* and finally save the result */
-	if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
-		*fb_div_p = fb_div / 10;
-		*frac_fb_div_p = fb_div % 10;
 	} else {
-		*fb_div_p = fb_div;
-		*frac_fb_div_p = 0;
-	}
-
-	*dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) +
-			(pll->reference_freq * *frac_fb_div_p)) /
-		       (ref_div * post_div * 10);
+               while (ref_div <= pll->max_ref_div) {
+                       avivo_get_fb_div(pll, target_clock, post_div, ref_div,
+                                        &fb_div, &frac_fb_div);
+                       if (frac_fb_div >= (pll->reference_freq / 2))
+                               fb_div++;
+                       frac_fb_div = 0;
+                       tmp = (pll->reference_freq * fb_div) / (post_div * ref_div);
+                       tmp = (tmp * 10000) / target_clock;
+
+                       if (tmp > (10000 + MAX_TOLERANCE))
+                               ref_div++;
+                       else if (tmp >= (10000 - MAX_TOLERANCE))
+                               break;
+                       else
+                               ref_div++;
+               }
+	}
+
+       *dot_clock_p = ((pll->reference_freq * fb_div * 10) + (pll->reference_freq * frac_fb_div)) / (ref_div * post_div * 10);
+       *fb_div_p = fb_div;
+       *frac_fb_div_p = frac_fb_div;
 	*ref_div_p = ref_div;
 	*post_div_p = post_div;
 
-	DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
-		      freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p,
-		      ref_div, post_div);
+       DRM_DEBUG_KMS("%d, pll dividers - fb: %d.%d ref: %d, post %d\n",
+                     *dot_clock_p, fb_div, frac_fb_div, ref_div, post_div);
 }
 
 /* pre-avivo */